1. Technical Field
The invention pertains to the field of connecting technology of electronic units. More particularly, the invention concerns a chip arrangement, a coupling component for contactless signal transmission between a first and a second chip, a chip for use in a chip arrangement, a wafer having a plurality of chip portions and a method of contactlessly coupling a first and a second chip together.
2. Discussion of Related Art
The demands on the connecting technology of electronic units are increasing due to rising clock rates. An example involving a very high level of significance is the communication between a processor and a main memory in computers. The interface between the processor and the main memory forms the essential bottleneck in terms of the growth of the computing power of the system. In the foreseeable future 64 bit processors with a clock rate of about 5 GHz are to be expected. They could service an interface to a main memory with a data rate of up to 320 Gbit/s.
One solution for the management of such high data rates would be to increase the internal cache memory of the processor to such an extent that at least during the execution of a thread there is always sufficient memory space available, in particular a block for interrelated code of usual size. It is thought that in this respect in the near future this will involve interconnected segments of some 10 B. A large internal cache will not be optimum in terms of surface area because of the technological demands for memories on a chip with a CPU. In addition the area of the memory considerably reduces the output of the processor overall.
An alternative solution involves providing a sufficiently powerful data path to external fast memory, for example in the form of SRAM (static random access memory). U.S. Pat. No. 6,496,889 B1 discloses a chip arrangement in which signals are sent from a first chip to a second chip by means of a capacitive coupling by way of a high-speed databus. For that purpose the housing in which the first and the second chip respectively is disposed is provided at the housing bottom with coupling elements in the form of metallically conductive strips. The housing is fitted on to a substrate which has a capacitively coupleable databus. The substrate also has metallic strips for coupling the signal in and out at the interfaces to the first and second chips. That enables a plurality of IC components to be arranged on the substrate and coupled together.
A disadvantage with the solution known from U.S. Pat. No. 6,496,889 B1 is coupling of the chips by way of a signal substrate which serves at the same time as a carrier for the chips and as a databus. That technology entails additional costs for production of the carrier. More specifically the signal substrate itself makes relatively high demands on the level of manufacturing accuracy so that it has to be manufactured with a technology which is close to the level of semiconductor technology. The price in relation to area of such a signal substrate is therefore relatively high.
The document K Kanda, D D Antono, K Ishida, H Kawaguchi, T Kuroda and T Sakurai, ‘1.27-Gbps/pin, 3 mW/pin Wireless Superconnect (WSC) Interface Scheme, ‘IEEE ISSCC Digest of Technical Papers, February 2003 pages 186-187 discloses a chip arrangement in which chips are arranged in mutually superposed relationship. A first chip has coupling surfaces which are distributed over the entire surface of its underside and a second chip has coupling surfaces which are distributed over the entire surface of its top side, these being referred to as mini-pads. The mini-pads are approximately square with a side length of 20 μm. Their mutual spacing is also 20 μM. The chips are so arranged relative to each other that a capacitive coupling is afforded between mutually associated mini-pads. For that purpose the chips are laid one upon the other in such a way that mutually associated coupling surfaces lie one upon the other. To produce the capacitive coupling the associated pads are arranged at a spacing of between 1 and 2 μm relative to each other. The surface of the mini-pads is provided with an oxide layer. In that way it is possible to dispense with further structures for protecting against electrostatic discharge (ESD). Thus the capacitance of a pair of pads is reduced, which improves signal transmission. A data rate of 1.27 Gbit/s per pad with 3 mW power loss was achieved.
A disadvantage of the previously known chip arrangements is the difficulty of implementing exact positioning of the chips relative to each other. Inaccuracies in manufacture and a rise in temperature of a chip in operation also result in errors in the position of the mini-pads relative to each other.
It is precisely for processors however that the thermal load-carrying capability must be very high. In order to guarantee an adequate coupling effect that entails high minimum values in regard to the size of the electrodes. Large electrodes limit the data rate due to capacitive loading of the signal path and a reduction in the number of possible data paths.
In addition relatively large pads occupy a large part of the available chip area for contactless coupling. That means that the mechanical structure of the chip in the housing is dominated by contactless coupling. Particularly in relation to processors a large proportion of the chip area is as a rule required for conventional connections and for cooling. Therefore the provision for example of an additional contactless coupling with the main memory chip is not compatible with the conventional area requirements. Contactless coupling in addition to conventional connecting processes for signal transmission cannot therefore be used in the processor area.
In actual fact further previously known solutions therefore provide using capacitive coupling as a complete replacement for previous connecting procedures. See in that respect D B Salzman, T F Knight, ‘Capacitively Coupled Multichip Modules’, Proceedings of the 1994 International Conference on Multichip Modules, April 1994, pages 487-494, or D Salzman, T Knight, ‘Capacitive coupling solves the known good die problem’, Proceedings of the 1994 Multi-Chip Module Conference, 1994, pages 95-100, or D B Salzman, T F Knight, ‘Manufacturability of capacitively coupled multichip modules’, IEEE Transactions on Components, Packaging, and Manufacturing Technology, Part B: Advanced Packaging, Vol 18, No 2, May 1995, pages 277-281, or D Salzman, T Knight, P Franzon, ‘Application of capacitive coupling to switch fabrics’, Proceedings of the 1995 Multi-Chip Module Conference, 1995, pages 195-199, or S Mick, J Wilson and P Franzon, ‘4 Gbps High-Density AC Coupled Interconnection’, IEEE 2002 CICC Digest of Technical Papers, May 2002, or K Kanda, D D Antono, K Ishida, H Kawaguchi, T Kuroda and T Sakurai, ‘1.27-Gbps/pin, 3 mW/pin Wireless Superconnect (WSC) Interface Scheme’, IEEE ISSCC Digest of Technical Papers, February 2003, pages 186-187.